FLEXIO2_CLK_SEL=FLEXIO2_CLK_SEL_0, CAN_CLK_SEL=CAN_CLK_SEL_0, CAN_CLK_PODF=DIVIDE_1
CCM Serial Clock Multiplexer Register 2
| CAN_CLK_PODF | Divider for CAN/CANFD clock podf. 0 (DIVIDE_1): Divide by 1 1 (DIVIDE_2): Divide by 2 2 (DIVIDE_3): Divide by 3 3 (DIVIDE_4): Divide by 4 4 (DIVIDE_5): Divide by 5 5 (DIVIDE_6): Divide by 6 6 (DIVIDE_7): Divide by 7 7 (DIVIDE_8): Divide by 8 8 (DIVIDE_9): Divide by 9 9 (DIVIDE_10): Divide by 10 10 (DIVIDE_11): Divide by 11 11 (DIVIDE_12): Divide by 12 12 (DIVIDE_13): Divide by 13 13 (DIVIDE_14): Divide by 14 14 (DIVIDE_15): Divide by 15 15 (DIVIDE_16): Divide by 16 16 (DIVIDE_17): Divide by 17 17 (DIVIDE_18): Divide by 18 18 (DIVIDE_19): Divide by 19 19 (DIVIDE_20): Divide by 20 20 (DIVIDE_21): Divide by 21 21 (DIVIDE_22): Divide by 22 22 (DIVIDE_23): Divide by 23 23 (DIVIDE_24): Divide by 24 24 (DIVIDE_25): Divide by 25 25 (DIVIDE_26): Divide by 26 26 (DIVIDE_27): Divide by 27 27 (DIVIDE_28): Divide by 28 28 (DIVIDE_29): Divide by 29 29 (DIVIDE_30): Divide by 30 30 (DIVIDE_31): Divide by 31 31 (DIVIDE_32): Divide by 32 32 (DIVIDE_33): Divide by 33 33 (DIVIDE_34): Divide by 34 34 (DIVIDE_35): Divide by 35 35 (DIVIDE_36): Divide by 36 36 (DIVIDE_37): Divide by 37 37 (DIVIDE_38): Divide by 38 38 (DIVIDE_39): Divide by 39 39 (DIVIDE_40): Divide by 40 40 (DIVIDE_41): Divide by 41 41 (DIVIDE_42): Divide by 42 42 (DIVIDE_43): Divide by 43 43 (DIVIDE_44): Divide by 44 44 (DIVIDE_45): Divide by 45 45 (DIVIDE_46): Divide by 46 46 (DIVIDE_47): Divide by 47 47 (DIVIDE_48): Divide by 48 48 (DIVIDE_49): Divide by 49 49 (DIVIDE_50): Divide by 50 50 (DIVIDE_51): Divide by 51 51 (DIVIDE_52): Divide by 52 52 (DIVIDE_53): Divide by 53 53 (DIVIDE_54): Divide by 54 54 (DIVIDE_55): Divide by 55 55 (DIVIDE_56): Divide by 56 56 (DIVIDE_57): Divide by 57 57 (DIVIDE_58): Divide by 58 58 (DIVIDE_59): Divide by 59 59 (DIVIDE_60): Divide by 60 60 (DIVIDE_61): Divide by 61 61 (DIVIDE_62): Divide by 62 62 (DIVIDE_63): Divide by 63 63 (DIVIDE_64): Divide by 64 |
| CAN_CLK_SEL | Selector for CAN/CANFD clock multiplexer 0 (CAN_CLK_SEL_0): derive clock from pll3_sw_clk divided clock (60M) 1 (CAN_CLK_SEL_1): derive clock from osc_clk (24M) 2 (CAN_CLK_SEL_2): derive clock from pll3_sw_clk divided clock (80M) 3 (CAN_CLK_SEL_3): Disable FlexCAN clock |
| FLEXIO2_CLK_SEL | Selector for flexio2/flexio3 clock multiplexer 0 (FLEXIO2_CLK_SEL_0): derive clock from PLL4 divided clock 1 (FLEXIO2_CLK_SEL_1): derive clock from PLL3 PFD2 clock 2 (FLEXIO2_CLK_SEL_2): derive clock from PLL5 clock 3 (FLEXIO2_CLK_SEL_3): derive clock from pll3_sw_clk |